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dc.contributor.authorPedroza de la Cruz, Adrian
dc.date.accessioned2020-08-07T17:34:38Z
dc.date.available2020-08-07T17:34:38Z
dc.date.issued2015
dc.identifier.urihttps://repositorio.cinvestav.mx/handle/cinvestav/626
dc.formatpdf
dc.format.extentxxi, 190 p. :28 cm.
dc.language.isospa
dc.publisherTesis (D.C.)--Centro de Investigación y de Estudios Avanzados del I.P.N. Unidad Guadalajara.
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subject.classificationINGENIERÍA Y TECNOLOGÍA
dc.subject.otherField programmable gate arrays
dc.subject.otherVerilog (Computer hardware description language)
dc.subject.otherComputer architecture
dc.subject.otherDissertations, Academic
dc.titleArquitectura reconfigurable de memorias para procesamiento en paralelo y aceleración de algoritmos
dc.typedoctoralThesis
dc.contributor.directorOrtega Cisneros, Susana
dc.identificator7
dc.identifier.marc01769cam a2200361 a 4500
dc.coverage.placeofpublicationGuadalajara, Jalisco, México
dc.description.institutionCINVESTAV
dc.description.unidadUnidad Guadalajara
dc.thesis.areaTecnología y Ciencias de la Ingeniería
dc.thesis.degreedisciplineDiseúo Electrónico.
dc.rights.accessopenAccess


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Except where otherwise noted, this item's license is described as http://creativecommons.org/licenses/by-nc-nd/4.0